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1/17 december 2004 this is preliminary information on a new product foreseen to be developed. details are subject to change without notice. vn920pep-e single channel high side driver rev. 3 table 1. general features cmos compatible input proportional load current sense shorted load protection undervoltage and overvoltage shutdown overvoltage clamp thermal shutdown current limitation protection against loss of ground and loss v cc very low stand-by power dissipation reverse battery protection (*) in compliance with the 2002/95/ec european directive description the vn920pep-e is a monolithic device designed in stmicroelectronics vipower m0-3 technology, intended for driving any kind of load with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes (see iso7637 transient compatibility table). figure 1. package active current limitation combined with thermal shutdown and automatic restart protect the device against overload. the device integrates an analog current sense output which delivers a current proportional to the load current. device automatically turns off in case of ground pin disconnection. table 2. order codes note: (*) see application schematic at page 10 type r ds(on) i out v cc vn920pep-e 15m ? 30 a 36 v powersso-24 ? package tube tape and reel powersso-24 vn920pep-e VN920PEPTR-E
vn920pep-e 2/17 figure 2. block diagram table 3. absolute maximum ratings symbol parameter value unit v cc dc supply voltage 41 v - v cc reverse dc supply voltage - 0.3 v - i gnd dc reverse ground pin current - 200 ma i out dc output current internally limited a - i out reverse dc output current - 40 a i in dc input current +/- 10 ma v csense current sense maximum voltage -3 +15 v v v esd electrostatic discharge (human body model: r=1.5k ? ; c=100pf) - input - current sense - output - v cc 4000 2000 5000 5000 v v v v p tot power dissipation t c 25c 96 w t j junction operating temperature internally limited c t c case operating temperature - 40 to 150 c t stg storage temperature - 55 to 150 c undervoltage overtemperature v cc gnd input output overvoltage current limiter logic driver power clamp v cc clamp v ds limiter detection detection detection k i out current sense
3/17 vn920pep-e figure 3. configuration diagram (top view) & suggested connections for unused and n.c. pins figure 4. current and voltage conventions table 4. thermal data note: (1) when mounted on a standard single-sided fr-4 board with 0.5cm 2 of cu (at least 35 m thick). note: (2) when mounted on a standard single-sided fr-4 board with 8cm 2 of cu (at least 35 m thick). symbol parameter value unit r thj-case thermal resistance junction-case max 1.3 c/w r thj-amb thermal resistance junction-ambient max 55 (1) 40 (2) c/w 1 2 3 4 5 6 output output output output input nc gnd v cc 24 23 22 21 20 19 nc nc output output tab = v cc 7 8 9 10 11 12 output output output output nc v cc nc current sense 18 17 16 15 14 13 nc nc output output connection / pin current sense n.c. output input floating x x x to ground through 1k ? resistor x through 10k ? resistor i s i gnd v cc v cc v sense output i out current sense i sense input i in v in v out gnd v f
vn920pep-e 4/17 electrical characteristics (8v 5/17 vn920pep-e electrical characteristics (continued) table 8. current sense (9v vcc 16v) (see figure 5) note: 2. current sense signal delay after positive input slope table 9. protections (see note 3) note: 3. to ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic sign als must be used together with a proper software strategy. if the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. symbol parameter test conditions min typ max unit k 1 i out /i sense i out =1a; v sense =0.5v; t j = -40c...150c 3300 4400 6000 dk 1 /k 1 current sense ratio drift i out =1a; v sense =0.5v; t j = -40c...+150c -10 +10 % k 2 i out /i sense i out =10a; v sense =4v; t j =-40c t j =25c...150c 4200 4400 4900 4900 6000 5750 dk 2 /k 2 current sense ratio drift i out =10a; v sense =4v; t j =-40c...+150c -8 +8 % k 3 i out /i sense i out =30a; v sense =4v; t j =-40c t j =25c...150c 4200 4400 4900 4900 5500 5250 dk 3 /k 3 current sense ratio drift i out =30a; v sense =4v; t j =-40c...+150c -6 +6 % i senseo analog sense leakage current v cc =6...16v; i out =0a;v sense =0v; t j =-40c...+150c 010 a v sense max analog sense output voltage v cc =5.5v; i out =5a; r sense =10k ? v cc >8v; i out =10a; r sense =10k ? 2 4 v v v sense h sense voltage in overtemperature conditions v cc =13v; r sense =3.9k ? 5.5 v r vsens eh analog sense output impedance in overtemperature condition v cc =13v; tj>t tsd ; output open 400 ? t dsense current sense delay response to 90% i sense (see note 2) 500 s symbol parameter test conditions min. typ. max. unit t tsd shut-down temperature 150 175 200 c t r reset temperature 135 c t hyst thermal hysteresis 7 15 c i lim dc short circuit current v cc =13v 5v vn920pep-e 6/17 electrical characteristics (continued) table 10. v cc - output diode figure 5. i out /i sense versus i out figure 6. switching characteristics (resistive load r l =1.3 ? ) symbol parameter test conditions min typ max unit v f forward on voltage -i out =5.3a; t j =150c 0.6 v 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 3000 3500 4000 4500 5000 5500 6000 6500 min.tj=-40c max.tj=-40c min.tj=25...150c max.tj=25...150c typical value i out (a) i out /i sense v out dv out /dt (on) t r 80% 10% t f dv out /dt (off) i sense t t 90% t d(off) input t 90% t d(on) t dsense
7/17 vn920pep-e table 11. truth table figure 7. switching time waveforms conditions input output sense normal operation l h l h 0 nominal overtemperature l h l l 0 v senseh undervoltage l h l l 0 0 overvoltage l h l l 0 0 short circuit to gnd l h h l l l 0 (t j t tsd ) v senseh short circuit to v cc l h h h 0 < nominal negative output voltage clamp ll 0 t t v outn v inn 80% 10% dv out /dt (on) t d(off) 90% dv out /dt (off) t d(on)
vn920pep-e 8/17 table 12. electrical transient requirements on v cc pin iso t/r 7637/1 test pulse test levels i ii iii iv delays and impedance 1 -25 v -50 v -75 v -100 v 2 ms 10 ? 2 +25 v +50 v +75 v +100 v 0.2 ms 10 ? 3a -25 v -50 v -100 v -150 v 0.1 s 50 ? 3b +25 v +50 v +75 v +100 v 0.1 s 50 ? 4 -4 v -5 v -6 v -7 v 100 ms, 0.01 ? 5 +26.5 v +46.5 v +66.5 v +86.5 v 400 ms, 2 ? iso t/r 7637/1 test pulse test levels results i ii iii iv 1cccc 2cccc 3acccc 3bcccc 4cccc 5c e e e class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
9/17 vn920pep-e figure 8. waveforms sense input normal operation undervoltage v cc v usd v usdhyst input overvoltage v cc sense input sense load current load current load current overtemperature input sense t tsd t r t j load current v ov v ovhyst v cc > v usd short to ground input load current sense load voltage input load voltage sense load current vn920pep-e 10/17 figure 9. application schematic gnd protection network against reverse battery solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1) r gnd 600mv / (i s(on)max ). 2) r gnd (? v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the device?s datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsd. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not common with the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on how many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the st suggests to utilize solution 2 (see below). solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd =1k ?) should be inserted in parallel to d gnd if the device will be driving an inductive load. this small signal diode can be safely shared amongst several different hsd. also in this case, the presence of the ground network will produce a shift ( j 600mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. this shift will not vary if more than one hsd shares the same diode/resistor network. series resistor in input line is also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating. safest configuration for unused input pin is to leave it unconnected, while unused sense pin has to be connected to ground pin. load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds v cc max dc rating. the same applies if the device will be subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. c i/os protection: if a ground protection network is used and negative transients are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of c and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of c i/os. -v ccpeak /i latchup r prot (v oh c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100v and i latchup 20ma; v oh c 4.5v 5k ? r prot 65k ? . recommended r prot value is 10k ?. v cc gnd output d gnd r gnd d ld c +5v r prot v gnd input current sense r sense r prot
11/17 vn920pep-e figure 10. off state output current figure 11. high level input current figure 12. input clamp voltage figure 13. input low level figure 14. input high level figure 15. input hysteresis voltage -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 0.5 1 1.5 2 2.5 3 3.5 4 il (off1) (a) -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 iih (ua) vin=3.25v -50 -25 0 25 50 75 100 125 150 175 tc ( c) 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 vicl (v) iin=1ma -50 -25 0 25 50 75 100 125 150 175 tc (c) 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 vil (v) -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 vih (v) -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 2 4 6 8 10 12 14 16 vhyst (v)
vn920pep-e 12/17 figure 16. overvoltage shutdown figure 17. turn-on voltage slope figure 18. on state resistance vs t case figure 19. i lim vs t case figure 20. turn-off voltage slope -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 30 33 36 39 42 45 48 51 54 57 60 vov (v) -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 dvout/dt (on)(v/ms) vcc=13v rl=1.3ohm -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 6 12 18 24 30 36 42 48 54 60 ron (mohm) vcc=13v iout=10a -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 10 20 30 40 50 60 70 80 90 100 ilim (a) vcc=13v -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 dvout/dt (off)(v/ms) vcc=13v rl=1.3ohm
13/17 vn920pep-e powersso-24 thermal data figure 21. powersso-24 pc board figure 22. r thj-amb vs pcb copper area in open box free air condition layout condition of r th and z th measurements (pcb fr4 area= 78mm x 78mm, pcb thickness=2mm, cu thickness=35 m, copper areas: from minimum pad lay-out to 8cm 2 ). 30 35 40 45 50 55 60 0123456789 rthj_a mb(c/w) pcb cu hea tsink are a (cm^2)
vn920pep-e 14/17 figure 23. powersso-24 thermal impedance junction ambient single pulse figure 24. thermal fitting model of a single channel hsd in powersso-24 pulse calculation formula table 13. thermal parameter 0.01 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth ( c/w) footprint 8 cm 2 area/island (cm 2 ) footprint 8 r1(c/w) 0.012 r2(c/w) 0.05 r3( c/w) 0.65 r4 (c/w) 4 r5 (c/w) 13.5 r6 (c/w) 37 22 c1(w.s/c) 0.0004 c2(w.s/c) 0.005 c3 (w.s/c) 0.022 c4 (w.s/c) 0.08 c5 (w.s/c) 0.7 c6 (w.s/c) 3 5 z th r th z thtp 1 ? () + = where t p t ? =
15/17 vn920pep-e package mechanical table 14. powersso-24? mechanical data figure 25. powersso-24? package dimensions symbol millimeters min typ max a 2.15 2.47 a2 2.15 2.40 a1 0 0.075 b 0.33 0.51 c 0.23 0.32 d 10.10 10.50 e7.4 7.6 e0.8 e3 8.8 g 0.1 g1 0.06 h 10.1 10.5 h 0.4 l 0.55 0.85 n 10deg x4.1 4.7 y6.5 7.1
vn920pep-e 16/17 revision history table 15. revision history date revision description of changes oct. 2004 1 - first issue. nov. 2004 2 - mechanical data updating. - powersso-24 thermal charact. insertion dec. 2004 3 - pc board copper area correction.
17/17 vn920pep-e information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this p ublication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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